The invention relates to high voltage circuits in integrated circuits (ICs). More particularly, the invention relates to a self-regulating high voltage ramp up circuit for an IC.
While most available ICs operate at fairly standard voltage levels (e.g., 3.3 volts, 2.7 volts, or 1.8 volts), some ICs require the application of significantly higher voltages on a temporary basis. For example, ICs that include static memory cells (e.g., PROMs, EPROMs, EEPROMs, and FLASH memory devices) require the application of high voltages to program values into the static memory cells. These ICs have special design requirements to avoid damaging the ICs during the application of the high programming voltages.
For example, a transistor programmed by the application of a high voltage typically has a thicker oxide and a longer channel length than a standard transistor. These attributes allow the high voltage transistor to handle the additional voltage without breaking down. For example, a given low voltage transistor might have an oxide thickness of about 33 Angstroms and a channel length of 0.18 microns and be able to handle up to 1.8 volts. However, a high voltage transistor on the same IC might have an oxide thickness of about 120 Angstroms and a channel length of 0.9 microns and be able to handle up to 15 volts.
For reliability reasons, it is desirable that a high voltage N-channel transistor not be exposed to a voltage switching very rapidly from zero volts to (for example) 15 volts. Similarly, a high voltage P-channel transistor should not be exposed to a voltage switching very rapidly from 15 volts to zero volts. Such rapid voltage alterations can stress the transistors undesirably, particularly if the voltage applications are repeated as the device is reprogrammed. By reducing the speed of the voltage transitions, the thick oxide and the transistor channels are protected from stress and the life of the device is extended.
Further, a very rapid voltage change at a high voltage node can cause a sympathetic change in other nodes located nearby. This inadvertent coupling effect can cause undesired changes of state in the nearby nodes, causing the device to function improperly.
Therefore, circuits and techniques have been developed to control and reduce the ramp up rate on output nodes driving high voltage transistors. While typical low voltage transistors turn on in the range of nanoseconds, the rise time of a high voltage node is preferably in the range of hundreds of microseconds, or even milliseconds.
FIG. 1 shows a typical waveform for a high voltage output node ramping up in a controlled fashion. The output node OUT is controlled by a series of delayed pulses initiated by enable signal EN, which goes high to the low voltage supply VDD at time TO. (voltage level VDD, the operating voltage, is referred to herein as the low voltage supply. Voltage level VPP, the programming voltage, is referred to herein as the high voltage supply. Typical values for VDD and VPP can be about 1.8 volts and 15 volts, respectively.) Each of the delayed pulses allows the voltage on output node OUT to increase by another small amount. Therefore, the resulting waveform resembles a xe2x80x9cstair-stepxe2x80x9d function, reaching the high voltage supply VPP at time T1. Ideally, the ramp up curve is as smooth and linear as possible, because minimizing the abrupt changes in voltage also minimizes the resulting stress on the IC.
FIG. 2 shows a typical high voltage ramp up circuit. In response to an enable signal EN, the prior art circuit of FIG. 2 generates a first clock signal CK using oscillator 201, where clock signal CK oscillates as long as the enable signal is high. Clock divider and phase generator 202 then slows down clock signal CK and uses the slowed clock signal to generate a series of phase-shifted clock signals PSCS. Phase-shifted clock signals PSCS are boosted to the high voltage level VPP using high voltage level shifter 203, producing high voltage phase-shifted clock signals HVPSCS.
At the same time, the circuit also boosts the enable signal EN to the high voltage level VPP, using high voltage level shifter 204. The resulting high voltage enable signal HVEN and the high voltage phase-shifted clock signals HVPSCS are used to control a complicated high voltage ramp up circuit 205, which generates the high voltage output signal OUT. Ramp up circuit 205 includes a charge pump, which necessitates the generation of the series of phase-shifted clock signals.
There are several drawbacks to the circuit of FIG. 2. Firstly, the circuit has a high current consumption, because each of blocks 201-205 in FIG. 2 consumes a significant amount of current. Secondly, and in some cases very importantly, the ramp up curve can vary significantly from the usual curve for this circuit (such as that depicted in FIG. 1). For the circuit of FIG. 2, the ramp up curve depends on the timing of the phase-shifted clock signals, and this timing is heavily dependent on variations in IC fabrication processing and operating temperature. Thus, the time required to reach the high voltage level VPP (Delta-T in FIG. 1) can vary widely. An IC product is guaranteed to operate at a certain speed at a given temperature. Therefore, a wide variation in the time required to program the static memory of an IC (an inevitable result of a wide variation in Delta-T) has an undesirable impact on the specifications for the IC product as a whole.
Therefore, it is desirable to provide a self-regulating high: voltage ramp up circuit having only minor variations in ramp up speed in response to changes in fabrication process and operating temperature. It is further desirable to provide a ramp up circuit having a low current consumption.
The invention provides self-regulating ramp up circuits that generate high voltage signals having a slow and smooth ramp up curve. The ramp up circuits of the invention have significantly lower current consumption, and the resulting output signals have reduced process and temperature variation relative to prior art circuits.
The circuits of the invention use a resistor and a capacitor to control the rate at which the output signal changes state. In some embodiments, the ramp up circuit forms a portion of a programmable logic device (PLD), and the resistor has a programmable resistance value. In some embodiments, the capacitor has a programmable capacitance value. This programmability allows a PLD user to select and program a ramp up rate for the high voltage output signal.
According to one embodiment, an enable signal operating at a low voltage level is shifted to the desired high voltage level using a level shifter. The resulting value is inverted using an inverter operating at the high voltage level. The circuit output node is also coupled to the high voltage power supply through an output pullup (e.g., a P-channel transistor) gated by the output node of the inverter. Thus, the inverter places a high value on the circuit output node when the enable signal goes high.
However, the goal of the output circuit is not just to drive the circuit output node high, but to do so slowly and in a controlled fashion. Therefore, the circuit output node is also coupled to the output node of the inverter through a capacitor, which reduces the rate at which the output node can be pulled up. The ramp up rate is further reduced by including a resistor in the pulldown path of the inverter, which restricts the rate at which the output pullup can be turned on.
In some embodiments, the pulldown path of the inverter includes an additional pulldown gated by a clock signal. The clock signal is generated by providing the enable signal to an oscillator, and providing the oscillator output signal to a clock divider. The clock divider output signal gates the additional pulldown. Therefore, the signal provided by the clock divider is an oscillating signal having a reduced frequency (in some embodiments a programmable frequency) that is active only when the enable signal is active. Hence, the pulldown path through the inverter allows current flow only a fraction of the time that it would without the additional pulldown, further reducing the ramp up rate of the output signal.
According to another embodiment, a self-regulating ramp up circuit includes a level shifter, first and second pullups, a pulldown, a resistor, and a capacitor. The first pullup is coupled between a power high terminal and an internal node, with a gate terminal coupled to the output terminal of the level shifter. The second pullup is coupled between the power high terminal and a slow ramp up output terminal, with a gate terminal coupled to the internal node. The capacitor is coupled between the internal node and the slow ramp up output terminal. The first pulldown and the resistor are coupled in series between the internal node and a ground terminal. The first pulldown has a gate terminal coupled to the output terminal of the level shifter.
In some embodiments, the resistor includes a resistance element and a second pulldown coupled in series, the second pulldown having a gate terminal controlled by a biasing signal at a voltage level between that of the power high terminal and ground. The second pulldown provides added resistance that is easily modified, and permits the use of a smaller resistance element.
According to another embodiment, a programmable logic device (PLD) includes a level shifter, first and second pullups, a pulldown, a resistor, and a capacitor, coupled together as described above. However, in this embodiment the capacitor has a programmable capacitance value based on configuration data for the PLD. In another embodiment, the resistor has a programmable resistance value based on configuration data for the PLD.